Multi-channel master: Use of the EnDat Master Basic
- EnDat Master Basic is supplied as EDIF netlist (encrypted VHDL code available on request)
- Register interface and APB interface are included
- To be provided by customer:
- Bus interface
- Low cost of design and testing Bus interface: e.g. APB to SPI is commercially available
- The number of logic elements (LE) is usually higher in comparison to a solution with EnDat Master Reduced
Multi-channel master: Use of the EnDat Master Reduced
- EnDat Master Reduced is supplied as VHDL code
- To be provided by customer:
- Register interface
- Bus interface
- The solution usually has fewer logic elements (LE) than does a solution with the EnDat Master Basic
- The register interface can be tailored to the customer's needs
- Higher cost of design and testing
Are HEIDENHAIN encoders designed for the cyclic storage of data?
For data storage, HEIDENHAIN encoders use so-called EEPROMs, which have a limited endurance due to their physical design. These encoders are thus of only limited suitability for the cyclical storage of data. For more information, refer to the EnDat Application Note.
The following RS-485 transceivers with fail-safe receivers are currently recommended by HEIDENHAIN, depending on the transmission frequency, temperature and supply voltage requirements. Identical blocks (same internal signal propagation time) must be used for clock and data:
These are the essential requirements on the RS-485 transceiver:
- For EnDat2.2, HEIDENHAIN recommends RS-485 transceivers with a data rate of at least 32 Mbps. This makes it possible to support the maximum clock frequency of 16 MHz defined for EnDat 2.2.
- For EnDat2.1, HEIDENHAIN recommends RS-485 transceivers with a data rate of at least 4 Mbps. This makes it possible to support the maximum clock frequency of 2 MHz defined for EnDat 2.1.
- The edge steepness of the driver (rise or fall time) must be <25 ns (for EnDat 2.1 and EnDat 2.2).
Application test under operating conditions:
In all cases, an application test must be conducted, taking into account the complete transmission distance (RS-485 transceiver, cable, connector, etc.). This also applies to the application-specific requirements for the operating conditions, including voltage supply, temperature, EMC and ESD.
Before accessing the memory, the MRS code for the desired range must always be set first. An MRS range remains set until
a) a new MRS range is selected
b) an EnDat 2.1 reset is sent
c) an EnDat 2.2 reset is sent
See also the EnDat Application Notes, Chapter “Sequences and data structures”
See also the “Sequences and data structures” chapter of the EnDat Application Note.
The two composite error bits F1 and F2 should be monitored in every query. F1 and F2 are generated independently of each other, and must be evaluated separately from each other. It is recommended that errors and warnings be buffered in the subsequent electronics before they are cleared (for diagnostic purposes at a later date, e.g. error log). Clearing of errors and warnings is basically possible with EnDat 2.1 and EnDat 2.2 commands. However, not all causes of errors can be reset within one communication cycle with the EnDat 2.2 command. In these cases the error messages can remain set. The following priorities for the clearing of errors are the result (the timing requirements of an application decide when the next priority stage is to be switched to):
- Stage 1: Clearing with EnDat 2.2 mode commands in the control cycle
Resetting of error causes that can be reset within one control cycle
- Stage 2: Clearing with EnDat 2.1 mode commands
Resetting of error causes that require the encoder to be re-initialized
- Stage 3: Switching the unit off and on again
Resetting of error causes that require the encoder to be entirely restarted
- Stage 1: Clearing with EnDat 2.2 mode commands in the control cycle
The group bit for warnings is transmitted with the additional data. The warning bit should be queried at regular intervals, even if the application does not require the processing of additional data.
Error handling of the interface:
Along with the CRC check there are three different types of errors, which should also be monitored continuously; see Attachment A2 of the EnDat specification.
Also see the “EnDat Monitoring Functions” section of the EnDat Application Note.
- Errors and warnings should be reset independently of each other; see the sequence “Clearing errors or warnings”.
- As long as the encoder outputs a group error bit, it must be assumed that the values transmitted by the encoder, particularly the position values, are erroneous.
- With incremental encoders certain error states can only be detected after traversing the reference mark(s).
- See the “How to get started” chapter in the EnDat Application Note
- See the “Implementation” section on the website
See also the EnDat Application Note, Chapter "Implementation Examples"
See also the EnDat Application Note, Chapter "EnDat Monitoring Functions"
Certain hardware and software combinations of the MASTERDRIVES inverters erroneously send a clock or entire clock-pulse group in the boot phase of the connected position measuring system. If the encoder is driven by a clock during the boot phase, this can lead to an interruption of the boot procedure and output of incorrect position values.
SIEMENS initiated a redesign of the MASTERDRIVES electronics (SBM 2) and developed appropriate software. These modifications will be available starting in December 2008. To ensure functional combinations of encoders and MASTERDRIVES for the transition period, HEIDENHAIN will modify, upon request, PCBs of the standard rotary encoders of the 35-mm and 56-mm series with optical scanning and deliver them in limited quantity. They can be distinguished by the index after the serial number according to the enclosure.
The following procedure is recommended to find out whether a combination of MASTERDRIVES and HEIDENHAIN encoder is functional:
- Compare the ID number and the index of the serial number (letter at the end of the serial number) of the HEIDENHAIN encoder on the ID label with the encoders included in the attached list. See also the two attached examples of HEIDENHAIN ID labels.
- If the index of the serial number is lower than the one indicated, please refer to your contact person within the HEIDENHAIN Sales department. Indicate the serial and ID numbers of the encoder and mention these FAQ.
- If the index of the serial number is equal or higher, there should be no problems with the MASTERDRIVES inverter.
|1st clock period:||The driver in the encoder is deactivated|
|2nd clock period:||The driver in the subsequent electronics is activated|
|3rd to 8th clock period:||Transmission of the mode word|
|9th clock period:||The driver in the subsequent electronics is deactivated|
|10th clock period:||The driver in the encoder is activated|
- Before the first position-value request, word 13 of the EnDat 2.1 parameters must be read out, so that the subsequent electronics can correctly determine the number of clock pulses to be sent. EnDat 2.1 commands must be used to read out the information.
- If not enough clock pulses are transmitted, then some information will not be available to the user, and the encoder hangs in the middle of the communication cycle. So under certain circumstances, the next communication will fail.
- If too many clock pulses are transmitted, then the encoder interprets this as a continuous clock. The encoder is then within a communication cycle again, and under circumstances the next communication will fail.
- The communication with the encoder may seem to be functioning, but if the timing changes slightly, for example, it will fail suddenly. Sporadic communication errors can also occur.
- In principle the memory is freely programmable. HEIDENHAIN does not have requirements for the contents of the programming.
- The memory is divided into four areas. These areas can be used either by the OEM (parameters of the OEM areas 1..4) or by the encoder manufacturer for compensation values (compensation values areas 1..4).
- The content of the compensation-value areas is not of interest to the user.
- The EnDat 2.1 parameters (words 9-12, interrogation of words 9 and 10 suffices) contain information on whether the OEM area is supported, and which addresses within an available area can be addressed.
- Different families of encoders support different OEM memory areas and different address areas. Therefore, the assignment of the OEM areas must be read out for each and every encoder.
- For this reason, the subsequent electronics should form addresses relative to the determined values, and not use absolute addresses. The programming must be adapted to the individual encoder.
(See also the EnDat Application Note, Chapter "OEM Memory Area".)
- After the encoder has been powered, error messages can be set. Also refer to the EnDat specification.
- Please refer to the "Procedure After Switch-On" section in Chapter 2 of the EnDat Application Note.
- Certain types of measuring devices, such as those with buffer battery backup or incremental encoders, require particular measures after switch-on; see also the corresponding chapter of the EnDat Application Note.
Other information regarding errors and warnings:
- The error word can be reset; individual error bits cannot be reset (see specification).
- Not every encoder supports all alarms. The alarms that are supported can be read out from the encoder. Alarms that are not supported should be masked out.
- This way the control can determine whether the errors "demanded" by the application are even supported.
- In the future, additional error messages may be used by HEIDENHAIN !
- Once write-protection has been activated, it cannot be rescinded.
- The encoder must be sent to the Service Department at HEIDENHAIN, where the write-protection can be removed.
See also EnDat Technical Information
with incremental signals
without incremental signals
with incremental signals
without incremental signals
≤ 8MHz (bzw. 16 MHz)
bold: Standard version
- Distinguishing features between EnDat 2.1 and 2.2:
- Supply voltage and clock frequency; not command set!
- The ordering designation is indicated on the ID label.
- In the future, EnDat 2.1 encoders (EnDat 01 or 21) will also be available with the EnDat 2.2 command set!
- The clock frequency is based on the properties of the encoder (especially for pluggable cable assemblies and EnDat 02)
- Service encoders: Caution with parameters !
- If the clock must be interrupted during communication, the clock level must be kept at low. The encoder would interpret a high level for > 10 µs (or > 1.25 µs with reduced recovery time) as the end of the recovery time I, and therefore as the end of the communication cycle.
- With the exception of the LC (max. 30 µs), the clock level can be held at low for several ms.
|EnDat 2.1||The maximum permitted clock frequency depends on the maximum cable length. This results from the answer from the control also needing to be read in within one clock. The encoder places the data on the line with the rising clock edge. It is recommended that the control assume the data with the rising clock edge of the subsequent clock.|
|EnDat 2.2||In order to increase the clock frequency, propagation delay compensation (see EnDat specification) is performed. After power-on, but before propagation delay compensation is performed, the clock frequency must be limited to 300 kHz.|
The EnDat interface provides the possibility to reduce the recovery time for EnDat 2.2 mode commands (see EnDat specification). The reduction of the recovery time makes the realization of very short cycle times possible. The reduced recovery time led to misunderstandings regarding the specification data:
- The reduction of the recovery time is only allowed for EnDat 2.2 mode commands. EnDat 2.1 commands must always be sent with the standard recovery time of 10 .. 30 µs.
- The reduced recovery time must only be set once, because the setting is stored in the EEPROM.
- If the reduction of the recovery time is set by the customer (see EnDat specification), then only mode commands (2.1 or 2.2) with high frequency may be sent after the first EnDat 2.2 mode command with high frequency (> 1 MHz) has been sent. Switching back to the slow frequency (< 1 MHz) and EnDat 2.1 mode commands can cause problems with certain encoders because this operating mode is not available
- If it is necessary to switch from high frequency (> 1 MHz) to low frequency, the following sequence should be followed:
1) Deactivation of all selected additional information
2) Transmission of an EnDat 2.1 command with high transmission frequency
3) Switchover to low transmission frequency
- The shortened recovery time should only be used if this is necessary for reducing the cycle times.
- If the reduced recovery time is used, only EnDat 2.2 mode commands should be used in closed-loop control operation.
- Avoid switching from high to low transmission frequencies.
In the diagram in the EnDat specification it appears as if, after sending the mode word, I have to keep the clock at LOW, wait at least the time tCAL, and then the start bit appears immediately with the first clock pulse. I tried that with an encoder, and it worked. Is this correct, or do I continually have to send clock pulses and poll the start bit? A waiting period of 1 ms must be maintained when switching.
Unfortunately this is an incorrect interpretation of the diagram. It cannot be guaranteed that the behavior you described applies to all different encoder models. The dashed lines in the diagram indicate that the clock must continue to be sent to the encoder. The start bit must be polled; i.e. clock pulses must be sent until the start bit is sent. That is what the dashed lines in the diagram indicate. The EnDat 2.1 specifications and the EnDat 2.2 specifications refer to Appendix A4 and Appendix A5, respectively, several times. The timing for the EnDat 2.1 position command is described in Appendix A4/A5. Continued clocking while polling the start bit is described there. The time tCAL indicates the earliest possible time at which the position value can be retrieved from the encoder. The start bit must be polled independently of tCAL.
Due to the new scope of features of the EnDat02 interface, several encoder parameters differ from those of the predecessor encoders. For example, the measuring step was reduced from 100 nm to 5 nm, the OEM area was expanded, ….
Because it is now possible to control the axis “purely serially” or “with sinusoidal signals,” the LC xx3 encoders have some special characteristics that must be noted for correct operation of the encoders.
EnDat 2.1 and 2.2 position requests
The time absolute linear encoders need for calculating the position values (tcal) differs depending on whether EnDat 2.1 or EnDat 2.2 mode commands are transmitted (see the encoder specifications). If the incremental signals are evaluated for axis control, then the EnDat 2.1 mode commands should be used. Only in this manner can an active error message be transmitted synchronously with the currently requested position value. EnDat 2.1 or EnDat 2.2 mode commands can be used for pure serial position-value transfer for axis control. Position requests with EnDat 2.1 take about 1 ms until the position values are available. For position requests with EnDat 2.2, the position values can be determined in about 5 µs. However, any active error message can then only be transmitted after a delay of approx. 1 ms, due to internal processing times. A one-time position request with EnDat 2.2 may not be performed.
Continuous clock (only possible with EnDat 2.1 position requests)
Is not supported.
A clock interruption during the LOW phase may not last longer than 30 ?s..
Interruption of an EnDat request
The subsequent position request is not valid, and the encoder reacts with error type I or II.
Invalid memory access (incorrect MRS code)
Interruption of an EnDat request Is at first acknowledged by the encoder with error type II. The subsequent position request transmits the last position value transmitted. No error message is output: EnDat 2.1 position request: One-time EnDat 2.2 position request: Up to 1 ms
Switching between EnDat 2.1 and EnDat 2.2 commands (either direction):
A waiting period of 1 ms must be maintained when switching.
See also "Procedure After Switch-On" in the EnDat Application Note, Chapter 2 "Sequences and Data Structures"
Build-up time of supply voltage until Up.min is reached should be > 10 V/sec.
The 1 Vpp incremental signals attain valid values after at most 1.3 sec.
The encoder can be recognized as an EnDat or SSI encoder by the logic level on the data line, after power has been switched on.
Clock pulse edges during t1 or t2 can interrupt booting; this can only be corrected by switching the encoder off and then on again.
A first EnDat request (falling edge) is permissible once t3 has ended after at least 1 ms (there is no maximum time limit). After the first clock pulse, the direction of data on the data line is reversed (this is why the data line is then at “high impedance”).
The encoder requires a defined reset: Falling edge + end of recovery time; For the duration of the low phase the following applies: 0.125 < tlow < 30 µs
t1: Boot or reset time of the EnDat encoder
t2: Initialization phase of the EnDat encoder
t3: Must be maintained for downward compatibility to EnDat 2.1
The supported encoder types can be taken from the “parameters of the encoder manufacturer,” word 14:
- Incremental linear encoder
- Absolute linear encoder
- Rotational incremental singleturn encoder
- Rotational absolute singleturn encoder
- Multiturn encoder
- Multiturn encoder with battery buffer
The EnDat additional information must be processed for the connection of incremental encoders; For details, see the EnDat Application Note. The EnDat Master light cannot be used.
-> See the EnDat Application Note, Chapter 2:
“The additional data is saved in the non-volatile memory of the encoder, and not in the EEPROM. This is necessary to be able to switch between the pieces of additional data within a control cycle. Each additional data was assigned its own MRC code so that only one mode command is necessary for switchover. An address must not be specified. Not all encoders provide the full range of additional data. The available additional data can be read out of the EnDat 2.2 parameter, words 0 and 1.”/p>
As a rule, only supported additional data should be selected. If additional data that is not supported is selected, EnDat error type III is issued (see the EnDat Specification). In rare exceptions, a CRC error can be issued instead during the transmission of the corresponding additional data.
Error bits F1 and F2 play a central role here; see also the EnDat Application Note, Chapter 2, in the section on “General information on the processing of error messages, warnings and error handling in the interface.” This means that an error reaction should be triggered in reference to F1 or F2. Information contained in the error or warning register or in the operating status error sources is complementary information. For more information, see the EnDat Application Note, Chapter 7.
Simultaneous reading of the error or warning register through additional data 1 and of the operating status error sources through additional data 2 is not defined for the EnDat 2.2 interface, and can result in incorrect information.
These encoders differ from encoders with gear-based revolution counters in particular regarding how error messages are handled as well as the referencing of the multiturn range. For details, see the appropriate chapter of the EnDat Application Note.
Maximum 40-bit data width for the position value.
Maximum 48-bit data width for the position value.
It is recommended that the maximum possible data widths be available, so that future generations of encoders can also be connected. The trend is towards ever higher resolutions.
32-bit data width
Definitively not enough. For example, the EQN 1337 has 12-bit multiturn and 25-bit singleturn resolution, for a total of 37 bits of position information.